IBM 990 podręczniki

Ibm 990 Instrukcja Użytkownika (284 strony)

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Spis treści

IBM zSeries 990

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Technical Guide

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May 2004

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Second Edition (May 2004)

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Contents

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Contents v

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Trademarks

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Become a published author

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Comments welcome

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1.1 Introduction

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1.2 z990 models

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1.3.1 Processor

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1.3.2 Memory

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1.3.6 Spanned channels

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1.3.7 I/O connectivity

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Up to 1024 ESCON channels

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FICON CTC function

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FICON Cascaded Directors

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OSA-Express

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Gigabit Ethernet

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1000BASE-T Ethernet

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Token Ring

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1.3.8 Cryptographic

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Internal Coupling (IC)

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1.3.11 Hardware consoles

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1.3.12 Concurrent upgrades

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Capacity BackUp (CBU)

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1.3.13 Performance

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1.3.15 Software

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1.3.16 Software support

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Software pricing

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1.3.17 Summary

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System structure and design

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STI Slots

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Memory cards

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Memory Cards

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Book 0Book 3 Book 1 Book 2

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MRU 0 MRU 1

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2.1.3 Memory

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2.1.4 Ring topology

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2.1.5 Connectivity

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Book upgrade

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Book front view

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STI connectors

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2.1.6 Frames and cages

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I/O cages

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2.1.7 The MCM

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Figure 2-11 MCM chip layout

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2.1.9 Summary

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2.2 System design

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2.2.2 Book design

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Memory Card

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MBA Card

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2.2.3 Processor Unit design

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Compression Unit on a chip

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Without BHT:

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With BHT:

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IEEE Floating Point

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Translation Lookaside Buffer

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Instruction grouping

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Extended Translation Facility

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Central Processors

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Internal Coupling Facilities

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Purpose of a zAAP

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System Assist Processors

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Reserved processors

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Application preservation

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Sparing rules

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2.2.5 Memory design

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Memory allocation

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Central storage (CS)

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Expanded storage (ES)

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2.2.6 Modes of operation

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Logical Partitioning overview

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Logically partitioned mode

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* ’ and then

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2.2.7 Model configurations

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Software models

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PU conversions

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Capacity Backup (CBU)

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Software model MSU values

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2.2.8 Storage operations

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ESA/390 mode

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ESA/390 TPF mode

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Coupling Facility mode

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Linux Only mode

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2.2.9 Reserved storage

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2.2.12 I/O subsystem

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2.2.13 Channel Subsystem

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I/O system structure

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3.1 Overview

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Figure 3-2 z990 I/O cage

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Domain I/O slots in domain

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I/O Cage

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CEC Cage

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STI-2 Extender card

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STI-3 Extender card

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2084-B16 CEC Cage

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I/O Cage 1 I/O Cage 2

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2084-D32 CEC Cage

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I/O Cage 1

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/O Cage 2

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3.3.1 I/O feature cards

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PCIXCC 0868

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PCICA 0862

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I/O Cage 1 - Front

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I/O cage slot

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PCHID numbers

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3.4 Connectivity

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Configuration rules notes

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Spanned and shared channels

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3.4.2 ESCON channel

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16-port ESCON channel sparing

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Channel Sparing

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3.4.3 FICON channel

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FICON Express SX feature

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3.4.4 OSA-Express adapter

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HiperSockets function

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ISC-3 link

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ICB-4 link

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ICB-3 link

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ICB-2 link

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IC links

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3.4.7 Cryptographic features

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Channel Subsystem

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LCSS 0, 1, 2, 3 30 30 1024

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Multiple Image Facility (MIF)

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Logical partition number

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Logical partition identifier

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MIF Image ID (MIFID)

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Logical partition name

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4.1.3 Channel spanning

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4.3 LCSS-related numbers

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Cryptography

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Chapter 5. Cryptography 121

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Programming

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Chapter 5. Cryptography 123

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5.3.2 The PCICA feature

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5.3.3 Configuration rules

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Chapter 5. Cryptography 127

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PCICA 6 2 12 16 30/30

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PCIXCC 4 1 4 16 30/30

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5.5 Software requirements

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Software support

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6.1 Operating system support

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6.2 z/OS software support

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G5, G6, z800, or z900

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Planned z/OS V1.6 support

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6.2.3 HCD support

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6.2.4 Automation changes

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6.2.5 SMF support

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6.2.6 RMF support

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6.2.7 ICKDSF requirements

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6.2.8 ICSF support

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Stand-alone dump

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Automation

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6.3 z/VM software support

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6.5 TPF software support

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6.6 Linux software support

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6.8 Workload License Charges

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Processor identification

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Channel to channel links

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Sysplex functions

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7.1 Parallel Sysplex

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High capacity

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Dynamic workload balancing

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Systems management

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Resource sharing

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Single system image

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Message Time Ordering

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External Reference ID

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Link Type z990 Max

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Peer mode links

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Meaning of PARTITION

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Function Setup

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Function

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7.3.1 Benefits

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7.3.2 CF structure duplexing

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7.3.3 Configuration planning

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CF to CF link

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CF structure duplexing

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7.4.1 GDPS/PPRC

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GDPS/PPRC HyperSwap™

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Planned HyperSwap

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Unplanned HyperSwap

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GDPS FlashCopy® V2 support

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7.4.2 GDPS/XRC

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Application

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IRD overview

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7.5.1 LPAR CPU management

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Value of CPU management

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Workload type Priority

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Unique LPAR cluster names

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7.5.6 References

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Capacity upgrades

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8.1 Concurrent upgrades

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Model upgrades

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Planned upgrades

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Unplanned upgrades

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Capacity upgrade functions

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CUoD for processors

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CUoD for memory

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+ Model upgrade

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CUoD for I/O

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Internet

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Activation

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Initiation

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Ordering

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$

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8.5 Capacity BackUp (CBU)

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CBU activation

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Image upgrades

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CBU deactivation

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CBU testing

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8.6 Nondisruptive upgrades

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8.6.1 Upgrade scenarios

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^ zSeries 990 Technical Guide

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8.7.1 Balanced system design

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Multi-book structure

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Book 0 Book 1

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8.7.2 Superscalar processors

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8.8 Capacity measurements

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LSPR workloads prior to z990

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LSPR workloads for z990

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CB-S 20% 10% 15% 17.5% 25%

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20%----20%

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20% 30% 20% 15% - 20%

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Workload type

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LSPR-Mix

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(Default)

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Environmental requirements

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9.1 Introduction

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9.2 Weights

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9.3 Dimensions

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Hardware Management Console

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G5/G6 Series

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different Hardware

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Token-Ring LAN

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Enterprise

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Ethernet LAN

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Token-Ring

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Remote operations

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Support Element

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Fiber optic cabling services

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Glossary 255

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Glossary 257

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ESCON channel

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Glossary 259

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Related publications

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Online resources

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Related publications 263

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Numerics

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(0.5” spine)

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0.475”<->0.873”

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250 <-> 459 pages

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zSeries 990

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