IBM PPC440X5 Instrukcja Użytkownika Pobierz pdf (Strona 518)

XER

Integer Exception Register

PPC440x5 CPU Core User’s Manual Preliminary

Page 518 of 589

regsumm440core.fm.

September 12, 2002

XER

SPR 0x001 User R/W

See Integer Exception Register (XER) on page 72.

Figure 10-50. Integer Exception Register (XER)

0SO

Summary Overflow

0 No overﬂow has occurred.

1 Overﬂow has occurred.

Can be set by mtspr or by integer or auxiliary

processor instructions with the [o] option; can be

reset by mtspr or by mcrxr.

1OV

Overflow

0 No overﬂow has occurred.

1 Overﬂow has occurred.

Can be set by mtspr or by integer or allocated

instructions with the [o] option; can be

reset by

mtspr, by mcrxr, or by integer or allocated

instructions with the [o] option.

2CA

Carry

0 Carry has not occurred.

1 Carry has occurred.

Can be set by mtspr or by certain integer arith-

metic and shift instructions; can be reset by

mtspr,bymcrxr, or by certain integer arithmetic

and shift instructions.

3:24 Reserved

25:31 TBC Transfer Byte Count

Used as a byte count by lswx and stswx; written

by dlmzb[.] and by mtspr.

0123 24 25 31

SO

OV

CA

TBC

1 2 ... 513 514 515 516 517 518 519 520 521 522 523 ... 589 590

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